The present invention relates to a semiconductor apparatus, and more particularly, it relates to a technology effectively used for a semiconductor apparatus equipped with a highly reliable semiconductor memory circuit of a large storage capacity.
With regard to a semiconductor memory, there are mainly a random access memory (RAM), and a read only memory (ROM). Among others, a dynamic RAM (DRAM) is most often used as a main memory of a computer. A memory cell for storage includes one capacitor, and a transistor for storing a charge therein, and reading the charge therefrom. This memory is suitable for a large-scale system, because it is realized as a RAM by a minimum number of components. Thus, such memories have been mass-produced at relatively low costs.
In the conventional DRAM, an information charge stored in the capacitor is lost by a pn junction (leakage) current present in the memory cell. Accordingly, before the loss, the memory cell is cyclically refreshed (reproducing and writing operations) to hold stored information. This cycle is called a refreshing period, which is currently around 100 ms. This period must be made longer as a storage capacity is increased more. That is, the leakage current must be suppressed, which has become increasingly difficult with device microfabrication. As a technology for omitting the refreshing operation, the inventors presented a PLED memory in U.S. patent application Ser. No. 09/806,582 filed on Apr. 2, 2001.